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Products & Licensing
  FM with RDS receiver IP is proven in FPGA. In particular, Xilinx Virtex IV FPGA based system is used to prove FM receiver IP. Synthesizable cores are delivered in a hardware description language such as Verilog HDL or VHDL. Mentioned FM with RDS receiver IP is following the SPR design-flow (synthesis, placement and route.).  
  Channel Mode Indicator. (Mono / stereo)
  Mono/stereo blend: Gradual change from mono to stereo, depending on signal.
  Stereo Output at 48 kbps
  Signal Strength Indicator.
  Fast Frequency Acquisition.
  Integrated FM-RDS Demodulator.
  RDS Decoder: 5bit Error burst correction capability.
  PSN (Program service Name)
  Date Hour and CT (clock time)
  Radio Text
  Language Identification code.
  Program Type name